1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and a semiconductor device. In particular, the present invention relates to a formation method of an element isolation region for electrically isolating semiconductor elements from each other that are formed on a semiconductor substrate.
2. Description of the Related Art
As a method for electrically isolating semiconductor elements from each other, what is frequently used is a method including a step of forming a trench between active regions where semiconductor elements are to be formed on a substrate, and a step of filling the trench with an insulating material, so as to form an STI (Shallow Trench Isolation). FIGS. 13 to 16 show formation steps of an STI according to a conventional technique.
First, on an entire surface of a semiconductor substrate 100, an insulating film 101 (thermal oxide film) serving as a pad layer, and a CMP (Chemical Mechanical Polishing) stopper film 104 (SiN film) are formed in this order. Next, on the CMP stopper film 104, a resist 207 is formed with a pattern having an opening portion at each element isolation region. Next, using the resist as a mask, as shown in FIG. 13, the insulating film and the CMP stopper film are etched.
Next, after the resist 207 is removed, using the CMP stopper film 104 as a mask, the semiconductor substrate 100 is etched, so as to form a trench 108. Thereafter, as shown in FIG. 14, by thermally oxidizing the exposed plane of the substrate in the trench, a trench thermal oxide film 110 is formed. Next, by depositing a field insulating film 114 over the entire surface, the trench is filled with the field insulating film.
Next, as shown in FIG. 15, until the CMP stopper film 104 is exposed, the field insulating film is planarized. Thus, an element isolation film 116 is formed in the trench. Next, the CMP stopper film 104 is removed by carrying out etching with hot phosphoric acid. Each projection portion of the field insulating film 114 is subjected to the isotropic etching with etchant containing hydrofluoric acid, such that an element isolation region 117 is formed, as shown in FIG. 16. Further, on the substrate having formed thereon the element isolation region, a gate oxide film 102 is formed by thermal oxidation.
In liquid crystal display apparatuses such as liquid crystal displays and liquid crystal television sets, high-voltage transistors are installed in liquid crystal drivers that drive a display operation of a liquid crystal panel. In a case where an STI is formed, and a high-voltage transistor is then formed on each active region resulted by the element isolation in accordance with the above-described conventional technique, the thickness of the gate insulating film must be increased in order for the transistor to operate withstanding a high voltage. However, as in the above-described conventional technique, when the STI is formed and thereafter the gate insulating film having a great thickness is formed on the semiconductor substrate by the thermal oxidation, the thickness of the gate insulating film is reduced particularly at the peripheral portion of the active region and the STI corner portion. This results in the presence of kink in the transfer characteristic of the transistor formed on the active region.
FIG. 1 is an SEM cross-sectional picture of an STI formed in accordance with the conventional technique, and FIG. 2 shows the relationship between a gate voltage Vg and a drain current Id of a transistor formed in accordance with the conventional technique. As shown in FIG. 1, it can be seen that the thickness of the gate oxide film (Gox) is reduced at the STI corner portion (encircled portion in FIG. 1). As a result, the characteristic of the transistor formed on the active region becomes a combination of respective characteristics of two types of transistors which are different in gate oxide film thickness. As shown in FIG. 2, when the substrate potential Vb is −2.5 to −7.5 [V], kink is observed in the relationship between the gate voltage Vg and the drain current Id (transfer characteristic), in the region where the drain current Id is 10−8 to 10−7 [A].
With the liquid crystal driver, such presence of kink in the transfer characteristic of the transistor causes incorrect gradation expression of a displayed image, which eventually leads to a poor image display performance of the liquid crystal display or the liquid crystal television set. Further, when the kink is significant, the leak current when the transistor is turned off becomes large, posing problems such as an increase in power consumption and heat emission.
One possible solution for such reduction in thickness of the gate oxide film at the STI corner portion may be the method disclosed in Japanese Unexamined Patent Application Publication No. 2004-247328 (hereinafter referred to as Document 1) that includes the steps of previously forming a gate insulating film on a semiconductor substrate; forming a CMP stopper film thereon; etching the gate oxide film and the CMP stopper film; and etching the semiconductor substrate to form a trench; forming a trench thermal oxide film; filling the trench with a field oxide film; and planarizing the field insulating film until the CMP stopper film is exposed. However, this method must overcome the following problems (1) to (3).
(1) When the thickness of the gate oxide film is increased, in the step of etching the semiconductor substrate to form the trench, the gate oxide film whose side surface is exposed is also etched simultaneously with the semiconductor substrate. Thus, as shown in the cross-sectional view of FIG. 3, a concave portion of the gate oxide film 102 under the CMP stopper film 104 becomes great. When the trench 108 is filled with the field insulating film 114 in this state, the concave portion cannot be covered. Even when it can be covered, as shown in FIG. 4, a void may possibly be formed in the element isolation film laterally positioned with respect to the gate oxide film. As a result of formation of the void, the dielectric strength voltage of the transistor formed on the active region becomes low.
(2) According to the disclosure of Document 1, when the CMP stopper film is removed by etching, dry etching having low selectivity (for example, about three) with respect to the gate oxide film is employed in removing the CMP stopper film, in order to lessen the damage done to the gate oxide film positioned under the CMP stopper film. However, in such a manner, the etching may not be stopped with the CMP stopper film, but the gate oxide film may also be etched. This may invite variations in the thickness of the gate oxide film of the active region. As a result, kink appears in the transfer characteristic of the transistor formed on the active region.
(3) Further, according to the disclosure of Document 1, in an attempt to prevent the stress applied to the STI by the high temperature associated with the formation of the well, the following steps are carried out: after formation of a well on a semiconductor substrate, forming a gate oxide film and a CMP stopper film; etching the gate oxide film and the CMP stopper film; etching the semiconductor substrate to form a trench; and forming an STI in the trench. In such a case, however, the formation of the STI on the well causes the additive impurity (in particular, boron) on the well to diffuse toward the STI, due to the thermal treatment step in the formation of the STI. Accordingly, the impurity concentration of the active region in the STI corner portion is reduced. Consequently, the characteristic of the transistor is impaired, by a reduction in the threshold voltage of the transistor and the presence of kink in the transfer characteristic and the like.
On the other hand, the object of the technique of Document 1 is to suppress the stress applied to the STI, to thereby suppress the crystal defect attributed to the STI stress, and Document 1 is silent about the effect on the characteristic of the transistor formed on the active region.